W25Q128JV PCB Design Guide: Footprint, Pinout, and Alternatives

The W25Q128JV is the 128 Mbit (16 MB) member of Winbond's JV-series QSPI NOR flash family, the workhorse that stores firmware on everything from Linux-capable embedded boards to data-logging MCU designs that need more than the 4 MB or 8 MB the smaller JV parts offer. It organizes 16M x 8 bits as 65,536 programmable pages of 256 bytes, speaks standard, dual, and quad SPI, and comes in six package families: SOIC-8 208-mil, SOIC-16 300-mil (with a dedicated /RESET pin), two WSON-8 footprints, TFBGA-24, and WLCSP.

The JV family has a split that matters at BOM time: IQ/JQ order codes have the QE bit factory-fixed to 1 (Quad enabled by default, backward compatible with the older FV family) and return JEDEC ID EF 40 18h, while IM/JM order codes have a programmable QE bit (factory-default 0), support DTR at 66 MHz and QPI mode, and return the newer device ID EF 70 18h. The IM/JM DTR and QPI features are documented in a separate datasheet; the base Rev G datasheet covers all four suffix types. All variants are rated 133 MHz at VCC 3.0–3.6 V and 104 MHz across the full 2.7–3.6 V range, with the legacy 03h Read Data instruction capped at 50 MHz.

The failure modes that bring people to this page are rarely inside the silicon. They are the IQ/JQ–IM/JM JEDEC ID mismatch that trips a bootloader, DTR expectations on a non-DTR variant, floating /WP and /HOLD pins that pause the interface at random, block-protect bits that survive power cycles and make a working chip look dead, and BOM substitutions from GigaDevice or Macronix the firmware does not recognize. Each is covered below.

What breaks boards

1. 01

   IQ/JQ and IM/JM variants return different JEDEC IDs

   IQ/JQ order codes return EF 40 18h via the 9Fh command (backward compatible with the legacy FV family), while IM/JM order codes return EF 70 18h. Bootloaders and flash drivers that match on the full three-byte JEDEC ID, such as RP2040 boot2 builds and ESP-IDF SPI flash drivers, will reject the wrong variant. Check which suffix your firmware expects before ordering, and verify that any second-source substitution matches the expected device ID bytes.

2. 02

   DTR and QPI are IM/JM-only; the base datasheet does not cover them

   Double Transfer Rate at 66 MHz and Quad Peripheral Interface mode are supported only on IM/JM variants and require the separate W25Q128JV DTR datasheet. IQ/JQ catalog entries show no DTR frequency listed, and the base Rev G datasheet directs readers to the DTR datasheet for those features. If your design needs DTR or QPI, you must order an IM or JM suffix part and use the DTR datasheet for timing and command details.

3. 03

   /WP, /HOLD, and /RESET must be driven or pulled high in plain-SPI use

   Left floating, /HOLD can pause the SPI interface mid-transaction and /WP can silently block status-register writes; the classic symptom is a flash that works on one board and hangs on the next. Pull both high (or tie them to VCC) in single or dual SPI mode. In quad mode these pins become IO2 and IO3, so route them as data lines if QSPI is on the roadmap. The SOIC-16 300-mil variant (code F) adds a dedicated /RESET pin that must also be handled; it is not present on the SOIC-8, WSON, or TFBGA packages.

4. 04

   A "bricked" flash is often just write-protected

   The block-protect bits (BP0–BP3, CMP, and SEC in the status registers) are non-volatile and survive power cycles. A protect configuration set by a previous bootloader, a factory image, or an errant write will persist indefinitely. If program and erase commands fail while reads work normally, read the status registers and clear the BP bits before assuming the chip is dead. Also check SR-1 bit 0 (BUSY/WIP) — the part may still be completing an internal erase or program cycle.

5. 05

   The RV series is the next-gen upgrade path; the JV series is still in production

   Winbond's W25Q-JV series page states that the W25Q-RV series offers up to 1.6× faster read speed on 58nm technology and is positioned as the recommended next-generation path for new designs. The JV series remains in active mass production across all 98 catalog variants, and its Rev G datasheet has not been revised since April 2019. For new designs, evaluate the RV series; for existing JV-based designs, the part is not going anywhere.

Key specifications

Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.

Alternatives

• W25Q32JV: Winbond's 32 Mbit member of the same JV family; same command set, same package footprint (SOIC-8 208-mil). Drop-in swap if 4 MB is enough; note the different JEDEC ID (EF 40 16h/EF 70 16h).
• W25Q256JV: Winbond's 256 Mbit JV family member (32 MB). Same interface and command set, same SOIC-8 208-mil footprint but uses 4-byte addressing mode for full access. Natural upgrade path when 16 MB is outgrown.
• GD25Q128E: GigaDevice's 128 Mbit equivalent; similar electrical specs and JEDEC ID bytes (C8 40 18h). Commonly substituted but bootloader ID and timing support must be verified on the target platform.
• MX25L12835F: Macronix's 128 Mbit equivalent; pin-compatible but different JEDEC manufacturer ID (C2h). Verify driver/bootloader support for its ID before BOM substitution.
• W25Q128RV: Winbond's newer RV-series (next-gen W25Q-JV successor, 58nm technology); up to 1.6× faster read speed. Consider for new designs but verify supply and compatibility with existing JV-based firmware.

Common questions

What is the difference between W25Q128JV IQ/JQ and IM/JM order codes?

IQ/JQ variants have the QE bit factory-fixed to 1 (Quad enabled by default, backward compatible with the older FV family) and return JEDEC ID EF 40 18h. IM/JM variants have a programmable QE bit (factory-default 0), support DTR at 66 MHz and QPI mode, and return the newer device ID EF 70 18h. If your bootloader or flash driver matches on the full JEDEC ID, the wrong variant will be rejected.

What do I do with the /WP and /HOLD pins on the W25Q128JV?

Pull them high. A floating /HOLD pin can pause the SPI interface mid-transaction, and a floating /WP pin can silently block status-register writes. In quad SPI mode these pins become IO2 and IO3, so route them as data lines to the host controller if QSPI is planned. The SOIC-16 300-mil variant (code F) also has a dedicated /RESET pin that must be handled.

Why does my flash fail to program or erase, but reads work fine?

Check the block-protect bits in the status registers. The BP0–BP3, CMP, and SEC bits are non-volatile and survive power cycles; a protect configuration set by a previous bootloader or factory image will persist. Read the status registers and clear the BP bits — the chip is write-protected, not broken. Also verify that /WP is pulled high.

Does the W25Q128JV support DTR (Double Transfer Rate)?

Only on IM/JM variants. DTR at 66 MHz and QPI mode are documented in the separate W25Q128JV DTR datasheet. IQ/JQ variants do not support DTR; their catalog entries show no DTR frequency listed. The base Rev G datasheet covers all variants and directs readers to the DTR datasheet for DTR and QPI details.

Is the W25Q128JV still in production? What about the RV series?

Yes, all 98 catalog variants are in mass production as of July 2026. The W25Q-RV series is Winbond's recommended next-generation upgrade with up to 1.6× faster read speed on 58nm technology. For new designs, evaluate the RV series; for existing JV-based designs, the JV series is not going anywhere and remains actively manufactured.