W25Q32JV PCB Design Guide: Footprint, Pinout, and Alternatives

The W25Q32JV is the 32 Mbit member of Winbond's ubiquitous serial NOR flash family — the chip that holds firmware next to an RP2040, stores web assets beside an ESP32, or logs data on anything with a spare SPI port. It organizes 4 M x 8 bits as 16,384 programmable pages of 256 bytes, speaks standard, dual, and quad SPI, and comes most commonly in SOIC-8 (150-mil SN and 208-mil SS codes, with VSOP and WSON options).

It is an active, current part: Winbond's Rev K datasheet was published in April 2026 and the parts catalog lists industrial order codes in production. One rating worth reading carefully — the 133 MHz maximum clock applies only with VCC between 3.0 and 3.6 V; at the 2.7 V end of the supply range the part is rated 104 MHz, and the plain 03h Read Data instruction is limited to 50 MHz regardless.

The failure modes that bring people to this page are rarely inside the chip. They are floating /WP and /HOLD pins, a 1.8 V JW part swapped into a 3.3 V design (or vice versa), firmware that ignores the 4 KB erase granularity, block-protect bits that survive power cycles, and second-source substitutions the bootloader does not recognize. Each is covered below.

What breaks boards

1. 01

   /WP and /HOLD must be pulled or driven high in plain-SPI use

   Left floating, /HOLD can pause the interface mid-transaction and /WP can silently block status-register writes — the classic symptom is a flash that hangs or ignores commands intermittently, working on one board and failing on the next. Pull both high (or tie them to VCC) whenever you use single or dual SPI. In quad mode these same pins become IO2 and IO3, so route them as data lines if QSPI is ever on the roadmap.

2. 02

   JV is the 3 V family — the 1.8 V part is W25Q32JW

   The W25Q32JV runs from 2.7 to 3.6 V; the pin-compatible W25Q32JW is the 1.8 V variant. The letter is easy to miss on a BOM line and the packages look identical, but powering a JW at 3.3 V or a JV at 1.8 V kills or brownouts the design. Check the suffix on the reel, not just the schematic symbol.

3. 03

   Write in 256-byte pages, erase in 4 KB minimum

   Program operations write 1 to 256 bytes within a single page, and the smallest erase is the 4 KB sector (20h), with 32 KB (52h), 64 KB (D8h), and chip erase above it. Firmware update and wear-leveling logic must respect this asymmetry: you cannot rewrite a byte in place, and erases dominate the time budget — a 4 KB sector erase runs 45 ms typical and up to 400 ms.

4. 04

   A "bricked" flash is often just write-protected

   The block-protect bits in the status register are non-volatile, so a protect configuration set once — by a previous bootloader, a factory image, or an errant write — persists across power cycles. If programs and erases fail while reads work, read the status registers and clear the BP bits before assuming the chip is dead.

5. 05

   Substituting other vendors: check the JEDEC ID, not just the pinout

   The W25Q32JV returns JEDEC ID EF 40 16 (Winbond EFh; note the -IM/JM order codes read 7016h instead). The GigaDevice GD25Q32E is electrically a drop-in and returns C8 40 16 — identical device and capacity bytes, different manufacturer byte. Bootloaders that match the full ID, such as RP2040 boot2 builds and ESP-IDF flash drivers, need explicit support for the substitute vendor, and per-bootloader timing and feature support is design-specific — verify on your target before switching the BOM.

6. 06

   133 MHz is conditional — read the clock fine print

   The headline 133 MHz clock (fC1) is specified for VCC from 3.0 to 3.6 V; across the full 2.7 to 3.6 V range the rating is 104 MHz (fC2). The legacy 03h Read Data instruction is limited to 50 MHz — use Fast Read variants above that. Dual and quad I/O reads give the equivalent of 266/532 MHz of single-line throughput at the same clock.

Key specifications

Verified against the manufacturer datasheet on 2026-07-09. Confirm the current revision before production use.

Alternatives

• W25Q128JV — four times the capacity in the same footprint with the same command set — the usual upgrade path when firmware outgrows 4 MB.
• GD25Q32E — GigaDevice's drop-in with matching device/capacity JEDEC bytes (C8 40 16 vs Winbond's EF 40 16) and close nominal timings; bootloader ID and timing support is design-specific, so verify on your target.
• MX25L3233F — Macronix's 32 Mbit equivalent; check driver and RP2040 boot2 support for its JEDEC ID before substituting.

Common questions

What do I do with the W25Q32 /HOLD pin?

Pull it high. A floating /HOLD pin can pause the SPI interface mid-transaction and cause intermittent hangs. If you plan to use quad SPI, that pin becomes IO3, so route it as a proper data line to the host controller instead of hard-strapping it.

Does the W25Q32 /WP pin need a pull-up?

Yes, in single or dual SPI keep /WP pulled or tied high, or status-register writes can be blocked. Also note the block-protect bits are non-volatile: if writes fail while reads work, read the status register and clear the BP bits — the chip is usually write-protected, not broken.

What is the difference between W25Q32JV and W25Q32JW?

Supply voltage. The JV runs from 2.7 to 3.6 V (with 3.0 to 3.6 V required for 133 MHz operation); the JW is the 1.8 V variant. They are pin-compatible and visually identical, so check the part-number suffix on the actual device before powering a board.

How do I wire the W25Q32 for quad SPI?

In quad mode the /WP and /HOLD pins are repurposed as IO2 and IO3, giving four data lines alongside clock and chip select. That means they can no longer serve their write-protect and pause functions, and all four IO lines need clean routing to the host's QSPI controller. Quad I/O reads deliver the equivalent of 532 MHz of single-line throughput at the max clock.