RP2040 PCB Design Guide: Footprint, Pinout, and Alternatives
Dual Cortex-M0+ 133 MHz MCU with 264 KB SRAM and external QSPI flash.
The RP2040 is Raspberry Pi's first microcontroller: two Cortex-M0+ cores at up to 133 MHz, a generous 264 kB of SRAM, 30 GPIO, full-speed USB, and the PIO state machines that let it bit-bang protocols most MCUs need dedicated silicon for. It comes in a single 7 × 7 mm QFN-56 and is unusually cheap for what it does. Raspberry Pi has committed to keeping it in production until at least January 2041, which removes the usual lifecycle anxiety around designing in a young part.
The defining design decision is that the RP2040 has no internal flash. Every board must pair it with an external QSPI NOR flash chip, and the boot ROM plus a flash-specific second-stage bootloader bring it up from there. This makes the minimal circuit slightly larger than an STM32's, but it also means flash size is your choice, and the USB mass-storage boot ROM makes the chip close to unbrickable.
The failure modes on RP2040 boards are well mapped: an unsupported or mis-configured flash chip, no BOOTSEL recovery path, 5 V logic on non-tolerant pins, a sloppy crystal choice that breaks USB, and expecting precision from an ADC that was not designed for it. Raspberry Pi's hardware design guide plus the minimal design example cover most of this; the gotchas below summarize what actually bites.
What breaks boards
No internal flash — external QSPI NOR is mandatory
The RP2040 executes from an external QSPI flash chip (a W25Q-class NOR part on nearly every board). The boot ROM loads a 256-byte second-stage bootloader that must match the flash part's command set and timing, so stick to the flash chips on the approved list in Raspberry Pi's hardware design guide, or verify the boot stage-2 your SDK build selects supports your part. Route the six QSPI lines short and matched, and place the flash close to the chip.
Always design in a BOOTSEL button
Holding the QSPI CS line low at reset forces the boot ROM into USB mass-storage mode, where the chip enumerates as a drive and accepts a UF2 file — no programmer needed. A button (or even just a test pad) from QSPI CS to ground is the universal recovery path and makes the RP2040 nearly impossible to brick. Boards that omit it lose the platform's best feature; add the button plus a reset button and field recovery becomes trivial.
GPIO are not 5 V tolerant
The RP2040's I/O runs at 3.3 V and none of the pins tolerate 5 V. Level-shift any 5 V inputs — a BSS138-style MOSFET shifter for bidirectional lines or a simple divider for one-way signals. This trips people migrating from ATmega328P designs where the whole board ran at 5 V.
USB needs a tight 12 MHz crystal
The chip expects a 12 MHz crystal, and USB's clock tolerance budget means you should specify a 30 ppm-class part rather than a bargain crystal. Follow the load-capacitor values from the hardware design guide for your crystal's specified CL rather than copying another board's values. Marginal crystals show up as flaky USB enumeration that looks like a firmware bug.
The ADC is not precision, and the core regulator needs its own decoupling
The 12-bit, 500 ksps SAR ADC has documented DNL spikes at specific codes, giving an effective resolution of roughly 8.7 ENOB — fine for pots and battery monitoring, wrong for precision measurement, where an external ADC is the answer. Separately, the 1.1 V digital core is fed by the on-chip regulator (VREG, 100 mA max), which needs its own input and output decoupling per the design guide; skimping here causes instability at higher clocks.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Cores/clock | Dual Arm Cortex-M0+, up to 133 MHz (200 MHz supported at DVDD = 1.15 V) | RP2040 Datasheet, Chapter 1 features / Section 2.15.3 |
| SRAM | 264 kB on-chip, in 6 independent banks | RP2040 Datasheet, Chapter 1 features + Section 2.6.2 |
| GPIO count | 30 GPIO pins (4 usable as analogue inputs) | RP2040 Datasheet, Chapter 1 features |
| ADC channels/bits | 4 channels + internal temperature sensor, 12-bit, 500 ksps SAR | RP2040 Datasheet, Chapter 1 features / Section 4.9 |
| USB speed | USB 1.1 controller + PHY: Full Speed (12 Mbps) device, Full/Low Speed host | RP2040 Datasheet, Chapter 1 features + Section 4.1 |
| QFN size | 7 × 7 mm QFN-56 (reduced ePad size) | RP2040 Datasheet, Figure 3 pinout |
| Core voltage | DVDD nominal 1.1 V (on-chip VREG output 1.1 V, 100 mA max) | RP2040 Datasheet, Section 2.9.2 + pin descriptions |
Verified against the manufacturer datasheet on 2026-07-09. Confirm the current revision before production use.
Alternatives
- RP2350 — the successor: Cortex-M33 cores, security features, and the same SDK and toolchain — but it ships in QFN-60 (RP2350A) and QFN-80 (RP2350B), so it is not footprint-compatible with the QFN-56 RP2040. A software upgrade path, not a PCB drop-in, and still a young part.
- STM32G030 — internal flash and a simpler minimal circuit; single core, slower, and no PIO equivalent.
- ESP32-S3 — adds Wi-Fi and BLE if you need radio, at the cost of much higher power draw and RF layout work.
Common questions
- Does the RP2040 need external flash?
- Yes — it has no internal flash and boots from an external QSPI NOR chip such as a W25Q-series part. Use a flash chip from the approved list in Raspberry Pi's hardware design guide so the second-stage bootloader matches it, and place it close to the RP2040 with short QSPI routing.
- Are RP2040 GPIO pins 5 V tolerant?
- No. All I/O is 3.3 V and 5 V signals must be level-shifted before reaching any pin. Use a MOSFET-based shifter for bidirectional buses or a resistor divider for one-way inputs.
- What crystal does the RP2040 need for USB?
- A 12 MHz crystal with tight tolerance — specify a 30 ppm-class part — plus load capacitors sized for the crystal's rated CL per the hardware design guide. Loose crystals cause intermittent USB enumeration failures.
- Do I really need a BOOTSEL button on a custom RP2040 board?
- Design one in. Pulling QSPI CS low at reset puts the boot ROM into USB mass-storage mode, letting you reflash by dropping a UF2 file onto the drive it presents. It is the recovery path that makes the RP2040 nearly unbrickable — a button or test pad costs almost nothing.