CD4017 PCB Design Guide: Footprint, Pinout, and Alternatives
4000-series Johnson decade counter: ten decoded outputs, one high per clock, 3–18 V supply.
The CD4017 — in TI's current catalog, the CD4017B — is the 4000-series decade counter: a 5-stage Johnson counter whose ten decoded outputs go high one at a time, advancing on each positive clock edge, with a carry-out that completes one cycle every 10 clock input cycles for cascading. It runs from 3 to 18 V, idles at 0.04 µA typical quiescent current at 5 V, and its Schmitt-trigger clock input accepts arbitrarily slow edges. That combination has kept it in LED chasers, sequencers, and divide-by-N circuits for five decades, and TI still ships it in PDIP, CDIP, SOIC, SOP, and TSSOP on a datasheet inherited from Harris.
Pick it for supply flexibility and near-zero static draw: anything from 3 to 18 V works, and at 0.04 µA typical it can sit across a battery indefinitely. Do not pick it for drive or speed at logic voltages — at 5 V the outputs guarantee only 0.51 mA and the clock only 2.5 MHz. The CD74HC4017 does the same decoded-decade job on 2-6 V rails, much faster and with real output drive, and on a modern 5 V or 3.3 V board it is almost always the better part. The 4000-series original earns its keep on higher rails, where at 15 V guaranteed drive rises to 3.4 mA and decode delays fall to 85 / 170 ns.
The failure modes below are the classics of 4000-series CMOS, and the 4017 collects all of them: outputs an order of magnitude weaker than anything TTL-shaped, floating inputs that turn the counter into an antenna, a slow-edge guarantee that applies to only one of the two clocking pins, a runt pulse baked into the popular divide-by-N reset trick, and timing that quietly evaporates below 5 V.
What breaks boards
Outputs guarantee only ~0.5 mA at 5 V — buffer anything real
At VDD = 5 V the outputs guarantee just 0.51 mA of sink or source current (1 mA typical) while staying within the 0.4 V test condition of the rail. A directly wired LED lights only by dragging the output far out of spec, and any logic input sharing that line then sees an invalid level. Even at 15 V the guaranteed sink is 3.4 mA, and each output transistor is limited to 100 mW absolute maximum. Buffer real loads with a transistor or a ULN2803A, and let the 4017 switch gates, not current.
Never float CLOCK INHIBIT or RESET
Every input is a high-impedance CMOS gate and must be tied somewhere. A floating CLOCK INHIBIT or RESET picks up hand capacitance and mains hum, producing random resets and double counts that vanish when the probe touches the pin. It also breaks the quiescent spec: the 0.04 µA typical / 5 µA max figure at 5 V assumes valid input levels. Ground both when unused. And keep every input between -0.5 V and VDD + 0.5 V at under ±10 mA — a signal source that powers up before VDD forward-biases the input protection network.
Slow clock edges are fine on pin 14 — not on pin 13
The CLOCK input (pin 14) has Schmitt-trigger pulse shaping, and the datasheet rates its rise and fall time as unlimited, so an RC ramp or a slow sensor can clock it directly. That guarantee does not transfer to the other clocking mode: with pin 14 tied high and pin 13 used as a negative-edge clock, edges must be 15 µs or faster or the counter miscounts. And Schmitt shaping is not debouncing — a pushbutton emits a burst of fast, valid edges, so a switch-clocked 4017 skips states until you add an RC filter or a debounce flip-flop.
The divide-by-N reset trick emits a runt pulse
Feeding decoded output N back to RESET makes a divide-by-N counter, but output N must go high before it can clear the chip, so it emits a runt pulse roughly one reset propagation delay long — 265 ns typical, 530 ns maximum at 5 V — on every cycle. Edge-triggered logic on that line counts twice. Take the clean divided signal from carry-out or a lower decoded output, and honor the reset timing: 260 ns minimum reset pulse width and 400 ns reset removal time at 5 V, which the self-reset trick starts to violate near the maximum clock rate.
This is not an HC part: speed scales with VDD, not with hope
The guaranteed clock maximum is 2.5 MHz at 5 V, 5 MHz at 10 V, and 5.5 MHz at 15 V — the 5 / 10 / 11 MHz figures are typicals, and the spec is measured with respect to the carry output. Clock-to-decoded-output delay is 325 ns typical, 650 ns maximum at 5 V. Below 5 V TI publishes no timing at all, so a 3 V design is legal but uncharacterized. If a 5 V board needs megahertz clocks or fan-out, use the CD74HC4017; if staying 4000-series, raising VDD to 15 V cuts decode delay to 85 / 170 ns.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Supply voltage (recommended) | VDD 3 V min / 18 V max (for TA = full package-temperature range) | SCHS027C Rev C (Feb 2004), Recommended Operating Conditions table, p. 3-51 |
| Absolute maximum supply | DC supply-voltage range (VDD, referenced to VSS) -0.5 V to +20 V; input voltage range -0.5 V to VDD +0.5 V; DC input current, any one input +/-10 mA | SCHS027C Rev C (Feb 2004), Maximum Ratings, Absolute-Maximum Values, p. 3-53 |
| Clock input frequency | fCL max 2.5 MHz at VDD = 5 V, 5 MHz at 10 V, 5.5 MHz at 15 V (guaranteed min); 5 / 10 / 11 MHz typ; measured with respect to carry output line | SCHS027C Rev C (Feb 2004), Recommended Operating Conditions table, p. 3-51 + Dynamic Electrical Characteristics, Maximum Clock Input Frequency row, p. 3-54 |
| Quiescent device current | IDD 0.04 uA typ / 5 uA max at VDD = 5 V (25 C); 0.04 / 10 at 10 V; 0.04 / 20 at 15 V; 0.08 / 100 at 20 V; rises to 150 / 300 / 600 / 3000 uA max at +85 C and +125 C | SCHS027C Rev C (Feb 2004), Static Electrical Characteristics, Quiescent Device Current IDD Max rows, p. 3-53 |
| Output drive | IOL min 0.51 mA / 1 mA typ (VO = 0.4 V, VDD = 5 V, 25 C); IOH min -0.51 mA / -1 mA typ (VO = 4.6 V, VDD = 5 V, 25 C); at VDD = 15 V IOL min 3.4 mA / 6.8 mA typ (VO = 1.5 V); device dissipation per output transistor 100 mW abs max | SCHS027C Rev C (Feb 2004), Static Electrical Characteristics, Output Low (Sink) / Output High (Source) Current rows, p. 3-53 + Maximum Ratings, p. 3-53 |
| Propagation delay, clock to decode out | tPHL, tPLH 325 ns typ / 650 ns max at VDD = 5 V; 135 / 270 ns at 10 V; 85 / 170 ns at 15 V (TA = 25 C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kohm); carry out 300 / 600, 125 / 250, 80 / 160 ns | SCHS027C Rev C (Feb 2004), Dynamic Electrical Characteristics, Clocked Operation, Propagation Delay Time rows, p. 3-54 |
| Operating temperature range | -55 C to +125 C (package dissipation 500 mW for TA = -55 to +100 C, derate linearly at 12 mW/C to 200 mW at +125 C) | SCHS027C Rev C (Feb 2004), Maximum Ratings, Absolute-Maximum Values, p. 3-53 |
| Clock rise/fall time | trCL, tfCL unlimited (only if Pin 14 is used as the clock input); if Pin 13 is used as the clock input and Pin 14 is tied high (for advancing count on negative transition of the clock), rise and fall time should be <= 15 us | SCHS027C Rev C (Feb 2004), Recommended Operating Conditions table and footnote, p. 3-51 |
| Reset timing | Reset pulse width tRW min 260 ns at VDD = 5 V, 110 ns at 10 V, 60 ns at 15 V; reset removal time trem min 400 / 280 / 150 ns; reset-to-output propagation delay tPHL, tPLH (carry out or decode out lines) 265 ns typ / 530 ns max at 5 V, 115 / 230 ns at 10 V, 85 / 170 ns at 15 V | SCHS027C Rev C (Feb 2004), Recommended Operating Conditions table, p. 3-51 + Dynamic Electrical Characteristics, Reset Operation, p. 3-54 |
Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.
Alternatives
- CD4022B: the octal (divide-by-8) Johnson counter with 8 decoded outputs from the same datasheet and family, same 3-18 V supply range. Use it when 8 states are enough; everything on this page, including the weak outputs, applies.
- CD74HC4017: TI's HC-family remake of the same decoded-output function: 2-6 V supply, much faster and with far stronger output drive at 5 V logic levels. The default choice on any modern 5 V or 3.3 V board.
- HEF4017B: Nexperia's 4000-series 5-stage Johnson decade counter; pin- and function-compatible second source (its specs are not verified on this page).
Common questions
- Can the CD4017 drive LEDs directly?
- Not within spec at 5 V: guaranteed output current is 0.51 mA (1 mA typical) while holding a valid logic level, and a directly connected LED pulls the output far outside its 0.4 V test condition. Each output transistor is also rated 100 mW absolute maximum. At 15 V the guaranteed 3.4 mA (6.8 mA typical) can run a low-current indicator through a resistor; for anything brighter, buffer each output with a transistor or a ULN2803A.
- What is the maximum clock frequency of the CD4017?
- Guaranteed minimums are 2.5 MHz at VDD = 5 V, 5 MHz at 10 V, and 5.5 MHz at 15 V, measured with respect to the carry output. The typicals are 5 / 10 / 11 MHz, but typicals are not tested limits — design to the guaranteed numbers.
- Can the CD4017 run at 3.3 V?
- Yes — the recommended supply range starts at 3 V — but TI characterizes timing and drive only at 5, 10, and 15 V, so a 3.3 V design runs slower and weaker than the already-weak 5 V numbers (0.51 mA drive, 2.5 MHz clock guaranteed) with no datasheet limits to design against. On a 3.3 V logic board use the CD74HC4017, which is specified for 2-6 V supplies.
- How do I make a divide-by-N counter with a CD4017?
- Connect decoded output N to RESET: the counter clears to its zero count each time output N goes high, giving one cycle per N clocks. Beware the runt pulse on output N — roughly the 265 ns typical (530 ns max at 5 V) reset propagation delay — and take the divided output from carry-out or a lower decoded line instead. For division beyond 10, cascade parts via carry-out, which completes one full cycle every 10 clock input cycles.