74HC595 PCB Design Guide: Footprint, Pinout, and Alternatives

The 74HC595 is the standard way to add output pins to a microcontroller: an 8-bit serial-in, parallel-out shift register feeding an 8-bit D-type storage register with 3-state outputs. Bits arrive on SER with each SRCLK rising edge, an RCLK edge copies the shift register into the output latches in one glitch-free step, and the QH' pin cascades into the next device, so a long chain costs the same data, clock, and latch lines as a single chip. TI's SN74HC595 (datasheet SCLS041J, Rev. J) runs from 2 to 6 V, draws 8 µA max quiescent at 25 °C, and shifts at 25 MHz min over temperature at 4.5 V, far beyond what most chained wiring can carry cleanly.

The double-buffered architecture is the reason to pick it over a bare shift register like the 74HC164: outputs change only on the latch edge instead of rippling while bits shift through. What the '595 is not is a driver. Guaranteed output levels are specified at ±6 mA per pin at 5 V, and the whole package is limited to ±70 mA through VCC or GND, so it belongs in front of logic loads and series-resistored indicator LEDs, not relay coils or bright LED strings. That job goes to a TPIC6B595 or a ULN2803A behind the outputs. It is also output-only; its mirror image for reading banks of switches is the 74HC165.

Field failures with this part are rarely the silicon. They are a short list of repeat design mistakes: treating the ±35 mA absolute maximum as a drive rating, letting random power-up data reach the pins because OE is hardwired low, tying the two clocks together without accounting for the one-clock lag, feeding slow or floating control edges that double-clock the register, and skimping on decoupling and clock routing in daisy chains. Each is covered below.

What breaks boards

1. 01

   ±35 mA per output is a stress rating; design to ±6 mA

   Absolute Maximum Ratings allow ±35 mA continuous per output and ±70 mA total through VCC or GND. Those are damage thresholds, and TI's application section repeats 35 mA per output / 70 mA per package as hard load limits, not targets. The levels actually guaranteed in the electrical tables are measured at ±6 mA at VCC = 4.5 V (±7.8 mA at 6 V). Eight LEDs at typical indicator currents crowd the package budget and sag VOH, so size series resistors around 6 mA per output, or move real current into a TPIC6B595 or ULN2803A.

2. 02

   Outputs power up with garbage if OE is hardwired low

   The registers have no power-on reset, so the storage register wakes in an arbitrary state, and with OE grounded that state drives the pins until firmware shifts and latches real data. Harmless on an LED bar; not harmless on relays, gate drivers, or enable lines. Pull OE up to VCC with a resistor and drive it low from the MCU only after the first valid latch. SRCLR alone is not the fix: per the function table it clears the shift register only, and the cleared bits reach the outputs only after another RCLK rising edge.

3. 03

   Tied-together clocks make the outputs lag one clock

   Tying SRCLK to RCLK is legal — TI's timing note says so — but the shift register is then one clock pulse ahead of the storage register, so the pins always show stale data and the last bit of a frame never appears until an extra clock arrives. If you use the trick, send one clock more than you have bits. With separate lines the timing is generous: SRCLK's rising edge must lead RCLK's by only 19 ns min over temperature at 4.5 V (15 ns at 25 °C), so ordinary SPI-plus-latch-pin wiring just works.

4. 04

   Slow or floating edges double-clock the register

   These are plain CMOS inputs, and TI limits input rise and fall times to 500 ns at VCC = 4.5 V (1000 ns at 2 V, 400 ns at 6 V). An edge that loiters between VIL max 1.35 V and VIH min 3.15 V (4.5 V supply) can double clock: one intended SRCLK pulse becomes two shifts and the pattern walks off by a bit. RC-filtered clock lines and long unbuffered cables to LED panels are the classic sources. TI is equally explicit that every unused input — SRCLR and OE included — must be tied to VCC or GND, never floated.

5. 05

   Daisy chains fail at the layout, not the logic

   Every '595 in a chain hangs on the same SRCLK and RCLK nets; long runs and stubs ring, and one reflection on SRCLK is a phantom shift that corrupts every downstream byte. Keep clock traces short, route device to device rather than as a star, and give each package the recommended 0.1 µF bypass directly at its VCC pin. Derate speed with supply, too: fmax is only 5 MHz min at 2 V versus 31 MHz min at 4.5 V (25 °C), so low-voltage chains deserve a slower shift clock.

Key specifications

Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.

Alternatives

• TPIC6B595: the power version: same shift-register interface, but open-drain DMOS outputs rated 50 V and 150 mA continuous sink per channel. The right part when the '595's ±6 mA logic outputs meet relays, solenoids, or LED strings.
• SN74AHC595: drop-in AHC-family upgrade: faster and lower power than HC at the same 2–6 V range and pinout. Pick it when HC timing margins get tight.
• SN74HCT595: TTL-compatible input thresholds for 5 V systems driven by TTL or lower-voltage logic that can't reach HC's CMOS VIH.
• 74HC595 (Nexperia) / MC74HC595A (onsemi): pin-compatible multi-source equivalents of the same generic function. Specs are close but not identical, so qualify against the datasheet of the vendor you actually buy.

Common questions

How much current can a 74HC595 output source or sink?

Design to the rated ±6 mA per output at 5 V; that is where TI guarantees VOH and VOL (test conditions extend to ±7.8 mA at VCC = 6 V). The ±35 mA per-output and ±70 mA per-package figures are absolute maximum ratings, and TI's application section repeats them as limits never to exceed. For anything heavier — relays, LED strings, solenoids — use a TPIC6B595 (50 V, 150 mA per channel, open-drain) or put a ULN2803A behind the outputs.

Can I use the 74HC595 with a 3.3 V microcontroller?

Yes — run its VCC from the same 3.3 V rail; the part is specified from 2 V to 6 V and input thresholds scale with supply. What is marginal is driving a 5 V-supplied '595 from 3.3 V logic: VIH min is 3.15 V at VCC = 4.5 V, leaving essentially no noise margin. Use the SN74HCT595 for that case. The reverse direction is easy: inputs tolerate up to 5.5 V at any valid VCC, so 5 V signals into a 3.3 V-supplied '595 are within spec.

How fast can I clock a 74HC595?

The SN74HC595 shift clock is specified at 31 MHz min (38 MHz typ) at 25 °C and 25 MHz min over temperature, at VCC = 4.5 V with a 50 pF load. At 6 V it is 29 MHz min, but at 2 V only 5 MHz min. In practice long daisy-chain wiring, not the silicon, sets the ceiling; also keep clock edges faster than 500 ns at 4.5 V or you risk double clocking.

Why are my 74HC595 outputs one update behind my data?

Almost certainly SRCLK and RCLK are tied together. That is a documented mode, but the shift register runs one clock pulse ahead of the storage register, so the pins latch the previous state on every edge. Send one extra clock per frame, or spend the extra GPIO and pulse RCLK separately after shifting.