74HC165 PCB Design Guide: Footprint, Pinout, and Alternatives

The 74HC165 is the standard answer to "I need more digital inputs": an 8-bit parallel-load shift register that latches eight lines through the SH/LD pin and clocks them out one bit at a time on the QH serial output. It runs from 2 to 6 V, is guaranteed to at least 31 MHz at 4.5 V and 25 °C, drives ±4 mA at 5 V, and idles at 8 µA maximum quiescent current at room temperature; the Rev G datasheet update even extended the commercial part's temperature ceiling from 85 °C to 125 °C. Registers cascade by feeding one device's QH into the next device's SER, so eight or sixty-four switch inputs cost the same three MCU pins. Note that "74HC165" is a generic family number: this page covers Texas Instruments' SN74HC165 per datasheet SCLS116H, and Nexperia's and onsemi's versions carry their own limits under their own part numbers.

Pick the HC165 for cheap, read-only input expansion: DIP switches, keypads, limit switches, front panels, anything an MCU should scan over a serial link. It is the input-side complement of the 74HC595 output expander and talks happily to hardware SPI or a bit-banged three-wire interface. It is the wrong part when the serial line must be shared politely, because QH is push-pull with no 3-state — that job belongs to the 74HC589A — and the wrong part when the parallel load must be synchronous to the clock, which is the 74HC166's territory. It is also slow at the bottom of its supply range: at 2 V, guaranteed fmax drops to 6 MHz and propagation delay swells to 75 ns typical.

Board-level failures with this part are remarkably consistent, and almost none of them are the silicon's fault. The five below cover the recurring ones: treating CLK INH as a clean clock gate when it is functionally a second clock, hanging QH on a shared SPI bus, feeding slow RC-debounced edges into CLK and double-clocking the register, leaving unused parallel inputs floating or cable-run inputs unprotected, and budgeting timing against the 50 MHz typical instead of the derated minimum.

What breaks boards

1. 01

   CLK INH is a second clock, not a clean gate

   TI's datasheet says CLK and CLK INH are interchangeable: holding CLK low and taking CLK INH from low to high clocks the register exactly as a CLK rising edge does. Firmware that pauses a scan by toggling CLK INH at an arbitrary moment therefore shifts a phantom bit, and every read after that is rotated by one. The datasheet's rule is to change CLK INH to high only while CLK is high. If you never use the inhibit function, tie CLK INH to ground permanently.

2. 02

   QH is push-pull, not 3-state — it cannot share a MISO line unbuffered

   There is no chip select and no high-impedance state: QH drives the wire with its ±4 mA output stage at all times. Parallel several HC165s onto one MISO line, or share MISO with a genuine SPI peripheral, and you get bus contention the moment the other device talks. The clean topologies are a cascade — QH of each stage into SER of the next, one line back to the MCU — or a 3-state buffer gated by your chip select. If you want the 3-state serial output natively, that part is the 74HC589A.

3. 03

   Slow edges on CLK or SH/LD can double-clock the register

   HC-family inputs are plain CMOS gates with no hysteresis. The recommended operating conditions cap input transition rate at 500 ns/V at VCC = 4.5 V (1000 ns/V at 2 V, 400 ns/V at 6 V), and the table's own footnote warns that edges loitering in the threshold region risk double clocking. An RC-debounced pushbutton or a sagging optocoupler output on CLK misses that limit by orders of magnitude, and the symptom is maddening: reads that are occasionally rotated by one bit. Square slow edges up with a Schmitt-trigger stage such as a 74HC14 first.

4. 04

   Floating inputs read garbage; long cable runs need clamp-current protection

   Every unused parallel input must be tied to VCC or GND: a floating CMOS input drifts into the threshold region, pulls supply current far past the 8 µA quiescent maximum, and returns random data. Switch and keypad inputs need pull resistors too, since a switch is open most of the time. And when the A–H lines arrive over an off-board harness, transients beyond the rails dump current into the input protection diodes, which are rated for only ±20 mA — add series resistance sized to keep worst-case clamp current inside that limit.

5. 05

   Budget timing on derated minimums, not the 50 MHz typical

   The headline numbers are 31 MHz minimum and 50 MHz typical at 4.5 V and 25 °C, but across the full −40 °C to 125 °C range the same supply only guarantees 21 MHz. Drop the rail and it collapses further: 6 MHz minimum at 2 V, with CLK-to-QH propagation delay swelling from 15 ns typ / 30 ns max at 4.5 V to 75 ns typ / 150 ns max at 2 V. Set your SPI clock against the minimum for your actual rail and temperature, and remember every register in a cascade sees the same clock, so the worst corner bounds the whole chain.

Key specifications

Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.

Alternatives

• SN74HC166: the same 8-bit parallel-load function in the same HC family, but the load is clock-synchronous (the HC165's SH/LD load is asynchronous) and it adds a clear input. Pick it when loading must line up with the clock domain.
• SN74HC589A: 8-bit parallel-in serial-out with an input storage latch and a 3-state serial output — the part to use when the serial line is a genuinely shared SPI MISO and you don't want external gating.
• CD4021B: 8-bit static parallel-in serial-out shift register with a 3 V to 18 V supply range; tolerates far higher rails than the HC165's 6 V ceiling but is much slower than HC.

Common questions

Can I read a 74HC165 with hardware SPI?

Yes: pulse SH/LD low to latch the inputs, drive CLK from SCK, and connect QH to MISO. Two catches. First, bit H sits on QH as soon as the load completes, before any clock edge, so use an SPI mode that samples before the first shift or you lose the first bit. Second, QH has no 3-state, so give the chain a dedicated MISO input or buffer it. Keep SCK under the guaranteed fmax for your rail: 31 MHz at 4.5 V and 25 °C, 21 MHz over the full temperature range.

How do I daisy-chain multiple 74HC165s?

Connect QH of each upstream device to SER of the next device, bus CLK and SH/LD to all of them, and read the whole chain from the QH at the end; each added register adds 8 clock cycles per read. Tie the SER input of the first device in the chain to a defined level rather than leaving it floating, and keep the shared clock edges fast and clean — a slow or ringing CLK across a long chain invites the double-clocking failure described in the gotchas.

Does the 74HC165 work at 3.3 V?

Yes — the recommended supply range is 2 V to 6 V, so 3.3 V is in spec. TI characterizes timing only at 2 V, 4.5 V, and 6 V, though, so 3.3 V performance has to be bounded conservatively between the 2 V column (fmax 6 MHz min, propagation delay 75 ns typ / 150 ns max) and the 4.5 V column (31 MHz min, 15 ns typ / 30 ns max). Clock a 3.3 V design well below the 4.5 V rating.

What decoupling does a 74HC165 need?

TI's power-supply recommendation is a 0.1 µF bypass capacitor on the VCC pin, installed as close to the pin as possible, and every register in a cascade should get its own. It matters more than it looks: HC165 inputs frequently arrive over long switch harnesses that couple noise straight onto the board, and a clean rail is what keeps the threshold and timing margins in the tables above honest.