CP2102N PCB Design Guide: Footprint, Pinout, and Alternatives
USB-to-UART bridge with internal oscillator and 3 Mbaud throughput; 3 package options down to 3x3 mm QFN.
The CP2102N is Silicon Labs' USB-to-UART bridge in the USBXpress family, designed to eliminate firmware complexity for USB connectivity. It integrates a USB 2.0 full-speed function controller, transceiver, 48 MHz oscillator, and UART into a single chip — no external crystal, no external resistors, and no firmware development required. All customization (VID, PID, serial string, GPIO configuration) is done through Silicon Labs' Xpress Configurator GUI in Simplicity Studio.
Three package variants cover different size and feature tradeoffs. The QFN28 (5x5 mm) has 7 GPIOs and battery charger detection. The QFN24 (4x4 mm) adds a separate VIO pin for level-shifted I/O, letting you run the UART side at 1.71-3.6 V while USB-side VDD stays at 3.3 V. The QFN20 (3x3 mm) has 4 GPIOs in the smallest footprint. All three share the same datasheet and the same A02 silicon revision.
The CP2102N's competitive advantage is its driver maturity: royalty-free Virtual COM Port drivers ship for Windows, macOS, and Linux; they are WHQL-certified and generally install without user intervention. It is the recommended upgrade path from Silicon Labs' older CP2102 and CP2104, with larger FIFOs (512 bytes each direction), higher maximum baud (3 Mbaud), and more GPIOs than its predecessors.
What breaks boards
VREGIN, VDD, and VIO are three separate power domains — wire them correctly
VREGIN (3.0-5.25 V) is the input to the internal 5V-to-3.3V regulator. VDD (3.0-3.6 V) is the core supply and regulator output. On QFN24, VIO (1.71 V to VDD) is a separate I/O supply pin. If you are not using the internal regulator (e.g., powering from a 3.3 V rail), tie VREGIN directly to VDD. In bus-powered designs, VREGIN connects to USB VBUS. Getting any of these wrong produces a chip that powers up but fails to enumerate, or enumerates intermittently depending on host port behavior.
The QFN20 and QFN28 tie VIO = VDD internally — QFN24 exposes VIO separately
On QFN20 and QFN28, there is no VIO pin; the I/O supply is internally connected to VDD (3.0-3.6 V). On QFN24, VIO is an independent pin that can be as low as 1.71 V, enabling direct interface to 1.8 V or 2.5 V logic without level shifters. If you copy a QFN24 schematic for a QFN28 layout, the VIO pin disappears and your UART logic levels are now VDD, not your intended low-voltage rail. Consult the pin definitions in Sections 5.1-5.3 of the datasheet before selecting a package.
Revision A01 had nine silicon errata — specify A02 for new designs
The original A01 revision had bugs including enumeration failures (E108, E109), .NET IO exceptions when manually controlling RTS (E104), RS485 DE signal timing (E105), DTR/RTS not resetting on port close (E106), and SUSPEND pin misbehavior (E107). All are resolved in A02. The sole remaining active errata on A02 is CP2102N_E110 (USB D+/D- pins undefined for ~15 ms during power-on reset), which has a documented workaround using an NMOS transistor to pull D+ low during reset. Do not use A01 silicon in production.
VBUS pin voltage must not exceed VIO + 2.5 V — use a resistor divider
The VBUS sense pin has an absolute maximum rating of VIO + 2.5 V (Table 3.10). A direct 5 V USB VBUS connection would violate this when VIO is 1.71-3.6 V. The datasheet requires a resistor divider on VBUS to bring the voltage within spec and to meet the VIH threshold of VIO - 0.6 V for VBUS detection. Silicon Labs' recommended connection diagrams in Section 2.3 show this divider; copying a reference design that omits it risks device damage or unreliable VBUS detection.
Hardware flow control is mandatory above 1 Mbaud — skip it and you drop data
The CP2102N's 512-byte RX FIFO fills faster than the USB host can drain it at high baud rates. Without CTS/RTS hardware handshaking, the RX FIFO overruns and data is lost. The datasheet (Section 4.3.9) states handshaking is required above 1 Mbaud. RTS is asserted when the RX FIFO hits the FLOW OFF watermark of 448 bytes and de-asserted at the FLOW ON watermark of 384 bytes (128 bytes of hysteresis). These watermarks are configurable in Xpress Configurator. Software XON/XOFF handshaking works but cuts throughput to >330 kbytes/s vs >450 kbytes/s with hardware flow control.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Supply voltage (VDD) | 3.0 V min / 3.3 V typ / 3.6 V max | CP2102N DS Rev 1.5, Table 3.1 Recommended Operating Conditions, VDD row |
| Regulator input (VREGIN) | 3.0 V min / 5.0 V typ / 5.25 V max | CP2102N DS Rev 1.5, Table 3.1 Recommended Operating Conditions, VREGIN row |
| I/O supply (VIO) | 1.71 V min to VDD max; on devices without VIO pin, VIO = VDD | CP2102N DS Rev 1.5, Table 3.1 Recommended Operating Conditions, VIO row + Note 3 |
| Operating temperature | -40 to 85 degC | CP2102N DS Rev 1.5, Table 3.1 Recommended Operating Conditions, TA row |
| Baud rate range | 300 baud to 3 Mbaud; prescale = 4 for <=365 baud, prescale = 1 above 365 baud | CP2102N DS Rev 1.5, Section 4.2.1 Baud Rate Generation, Table 4.1 Data Formats and Baud Rates |
| Active current (VREGIN) | 9.5 mA typ at 115200 baud bidirectional; 13.7 mA typ at 3 Mbaud bidirectional | CP2102N DS Rev 1.5, Table 3.2 Power Consumption, Normal Operation rows |
| USB suspend current | 195 uA typ | CP2102N DS Rev 1.5, Table 3.2 Power Consumption, USB Suspend row |
| Internal oscillator | 48 MHz typ (47.3 min / 48.7 max); +/-0.25% accuracy; temperature sensitivity 45 ppm/degC typ | CP2102N DS Rev 1.5, Table 3.5 Internal Oscillator |
| TX and RX buffer size | 512 bytes receive buffer; 512 bytes transmit buffer | CP2102N DS Rev 1.5, Section 1 Feature List, UART bullet list |
| Internal 5V-to-3.3V regulator | VDD output 3.1 min / 3.3 typ / 3.6 V max; max output current 100 mA; dropout voltage 0.8 V max at 100 mA | CP2102N DS Rev 1.5, Table 3.6 5V Voltage Regulator |
| GPIO count by package | QFN28: 7 GPIOs (with battery charger detect); QFN24 and QFN20: 4 GPIOs (no battery charger detect) | CP2102N DS Rev 1.5, Table 1.1 Product Selection Guide |
| USB spec | USB 2.0 compliant; full-speed (12 Mbps); integrated transceiver and matching/pull-up resistors | CP2102N DS Rev 1.5, Section 4.1 USB Function Controller and Transceiver, Section 1 Feature List |
Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.
Alternatives
- CH340C: WCH's lower-cost USB-UART bridge with internal oscillator, SOP-16. Popular on budget dev boards. Max 2 Mbaud vs CP2102N's 3 Mbaud; requires a crystal on the older CH340G variant.
- FT232RL: FTDI's industry-standard USB-UART bridge, SSOP-28. Deepest driver/OS support and tooling, but ~3x the cost and the most counterfeited USB-UART chip in existence.
- CH9102F: WCH's newer USB-UART bridge at up to 4 Mbaud in QFN-24. Increasingly found on newer ESP32 dev boards as a CP2102N alternative.
- CP2104: Silicon Labs' previous-generation USB-UART bridge, pin-compatible with CP2102N QFN24. The CP2102N is the direct upgrade path with more GPIO, battery charger detect, and larger FIFOs.
Common questions
- What is the difference between the CP2102 and the CP2102N?
- The CP2102N is a newer, more capable chip. It adds an internal 48 MHz oscillator (no external crystal needed), 512-byte TX/RX FIFOs, up to 7 GPIOs, USB Battery Charger Detection, remote wakeup, and packages down to 3x3 mm QFN20. The older CP2102 requires an external crystal and a larger QFN28 package. Silicon Labs provides a porting guide (AN976) for migrating CP2102 designs to the CP2102N.
- Which package variant should I use?
- Use the QFN28 (5x5 mm) if you need 7 GPIOs or battery charger detection. Use the QFN24 (4x4 mm) if you need a separate VIO pin for level-shifted I/O (e.g., interfacing 1.8 V or 2.5 V logic). Use the QFN20 (3x3 mm) for the smallest footprint when 4 GPIOs suffice. All three share the same A02 silicon and the same datasheet.
- Does the CP2102N need drivers?
- Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for Windows, macOS, and Linux. The Windows drivers are WHQL-certified and ship through Windows Update. macOS includes a built-in driver. Linux kernel has had mainline CP210x support for years. You can also use the USBXpress direct-access driver if you prefer an API over a virtual COM port.
- Can I use the CP2102N without the internal regulator?
- Yes. If your board already has a clean 3.3 V rail, tie VREGIN directly to VDD and power both from your 3.3 V supply. Make sure your VDD rail stays within 3.0-3.6 V. Do not leave VREGIN floating — it must be tied to VDD when the regulator is not used.
- How do I customize the VID/PID and serial number?
- Use Silicon Labs' Xpress Configurator in Simplicity Studio (free download). It reads and writes the CP2102N's internal 960-byte programmable ROM via USB. You can set custom VID, PID, product/manufacturer strings, serial number, power descriptor, GPIO behavior, and more. The configuration can be locked to prevent later modification. A unique VID/PID is recommended for commercial products to avoid driver conflicts.