AP63203WU-7 PCB Design Guide: Footprint, Pinout, and Alternatives
Wide-input 3.8–32 V, 2 A synchronous buck converter with fixed 3.3 V output, 1.1 MHz switching, integrated MOSFETs, and enhanced EMI reduction.
The AP63203 is Diodes' no-nonsense 3.3 V rail generator: 3.8 V to 32 V in, 2 A continuous out, two integrated MOSFETs (125 mΩ high-side, 68 mΩ low-side) switching at a fixed 1.1 MHz, all inside a 2.9 × 2.8 mm TSOT26. The output is fixed at 3.3 V — no resistor divider, no math, no trim — and the compensation network lives on chip. You bolt on an inductor, a BST capacitor, and a handful of ceramic caps, and the rail just works. That simplicity, plus 22 µA quiescent current and ±6% frequency spread-spectrum for EMI, makes it the default answer for a compact 3.3 V point-of-load regulator off a 12 V or 24 V bus.
The parts you do not need tell the story. There is no catch diode because the low-side MOSFET is integrated and synchronous — conduction losses are set by a 68 mΩ switch, not a Schottky's VF. There is no feedback divider because the output is factory-trimmed to 3.3 V ±1%. There is no compensation network to tune because the loop is internally compensated peak current mode. And there is no snubber on the switch node because Diodes' multi-level gate driver suppresses ringing without slowing down the edges. The result is a BOM of about six parts that passes CISPR 25 with margin.
The tradeoffs are small but real. The TSOT26 package has θJA of 89 °C/W — fine for 2 A at moderate ambient, but at 85 °C you will be derating hard without 2 oz copper and generous ground pours on both layers. The 1.1 MHz frequency is fixed; you cannot synchronize it. The device enters PFM at light loads by design (AP63203 is the PWM/PFM variant), which gives 88% efficiency at 5 mA but also means the switching frequency drops and the output ripple grows at no-load. If you need forced PWM at all loads for noise-sensitive analog, reach for the AP63201 instead. Pick the AP63203 when you need a predictable 3.3 V rail with minimal design effort; pick something else when you need output voltage flexibility, synchronization, or sub-10-µA quiescent current for always-on battery duty.
What breaks boards
The BST capacitor is 100 nF, not the 10 nF that other bucks expect
A 100 nF ceramic capacitor is required between BST and SW to power the high-side gate driver. This is an order of magnitude larger than the 10 nF BOOT cap on parts like the TPS5430. If the BST voltage falls below 2.3 V, the boot undervoltage protection forces Q2 on for 220 ns to refresh it — a hiccup you can see as erratic switching if you skimped on the cap. A 100 nF X7R with a voltage rating above VIN + 6 V handles all conditions. Do not substitute a 10 nF part from another buck design.
Fixed 3.3 V output means the FB pin is NOT a feedback divider — connect it directly to the output
The AP63203 is factory-trimmed to 3.3 V. The FB pin is a sense input, not a divider node; connect it directly to the output rail. There is no R1/R2 divider, no equation, and no way to adjust the output voltage. If you treat FB like an adjustable regulator's feedback pin and hang a divider on it, the internal reference loses regulation and the output goes wherever the divider pulls it. If you need an adjustable output, use the AP63200 (500 kHz) instead.
89 °C/W θJA in TSOT26 demands a thermal layout, not a placeholder
At 2 A out with 12 V in and 3.3 V out, the converter dissipates roughly 0.5–0.7 W. With θJA of 89 °C/W on a single-layer FR-4 board, that is a 44–62 °C junction rise over ambient — at 85 °C ambient you are already kissing the 125 °C recommended limit before any margin. Diodes' PCB layout section explicitly calls for 2 oz copper on both layers, a solid bottom-layer GND pour under the IC, and sufficient vias stitched through the input and output capacitor GND pads to pull heat into the backside plane. A 1 oz, two-layer board with a skinny ground pour will thermally throttle at sustained 2 A. Follow the datasheet's recommended layout in Figure 25.
PFM at light loads: the output ripple grows when the load drops
The AP63203 enters PFM below approximately 450 mA peak inductor current. In PFM the low-side MOSFET turns off at zero inductor current, and the converter skips pulses to maintain regulation. Efficiency reaches 88% at 5 mA, but the output ripple amplitude increases because switching becomes intermittent. If your downstream circuitry cannot tolerate the larger ripple, either size the output capacitance to absorb it (Diodes recommends 2 × 22 µF ceramics) or switch to the AP63201, which forces PWM at all loads. This is not a defect — it is the PFM variant doing what it was designed to do.
The enable pin has a precision 1.18 V threshold — use it for UVLO, not just on/off
The EN pin threshold is tightly specified: logic high at 1.18 V typ (1.15–1.23 V) and logic low at 1.10 V typ (1.05–1.15 V), with only 80 mV of hysteresis. An internal 1.5 µA pull-up lets you float EN for always-on operation. But the real value is that you can program a precise input UVLO with a two-resistor divider from VIN to EN, using the internal 4 µA hysteresis current source. The datasheet gives equations Eq.1 and Eq.2 for R5 and R6; a divider that enables the converter at 9 V and disables at 7 V prevents deep-discharge brownout, which is better than relying on the internal 3.5 V UVLO alone. Do not leave EN floating if your input supply has a slow ramp — use the divider.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Input voltage range | 3.8 V min / 32 V max; absolute maximum 35 V DC (40 V for 400 ms transient) | DS41326 Rev 3, Recommended Operating Conditions + Absolute Maximum Ratings |
| Output voltage (fixed) | 3.3 V fixed; 3.27 V min / 3.30 V typ / 3.33 V max in CCM at TA = 25°C, VIN = 12 V | DS41326 Rev 3, Electrical Characteristics, VFB for AP63203 |
| Output current | 2 A continuous output current; HS peak current limit 2.5 A min / 2.8 A typ / 3.1 A max; LS valley current limit 2.5 A min / 3.2 A typ / 3.9 A max | DS41326 Rev 3, Features + Electrical Characteristics, IPEAK_LIMIT / IVALLEY_LIMIT |
| Switching frequency | 1100 kHz (1.1 MHz) typ; Frequency Spread Spectrum (FSS) ±6% jitter for EMI reduction | DS41326 Rev 3, Features + Electrical Characteristics, fSW / FSS |
| Power MOSFETs (on-resistance) | High-side (Q1): 125 mΩ typ (integrated); Low-side (Q2): 68 mΩ typ (integrated); synchronous rectification — no external catch diode needed | DS41326 Rev 3, Features + Electrical Characteristics, RDS(ON)1 / RDS(ON)2 |
| Quiescent / shutdown current | IQ 22 μA typ (VEN = OPEN, VFB = 1.0 V, non-switching); ISHDN 1 μA typ / 3 μA max (VEN = 0 V) | DS41326 Rev 3, Electrical Characteristics, IQ / ISHDN |
| Minimum ON time | 80 ns typ — supports high step-down ratios even at 1.1 MHz switching frequency | DS41326 Rev 3, Electrical Characteristics, tON |
| Enable / UVLO | EN logic high 1.15 V min / 1.18 V typ / 1.23 V max; EN logic low 1.05 V min / 1.10 V typ / 1.15 V max; internal UVLO rising 3.30 V min / 3.50 V typ / 3.70 V max with 440 mV hysteresis; programmable UVLO via external resistive divider on EN pin | DS41326 Rev 3, Electrical Characteristics, VEN_H / VEN_L / UVLO |
| Soft-start | Fixed 4 ms internal soft-start period | DS41326 Rev 3, Electrical Characteristics, tSS |
| Thermal characteristics | θJA 89 °C/W, θJC 39 °C/W (TSOT26 on FR-4 single-layer); operating junction -40 to +125 °C; thermal shutdown +160 °C typ with +25 °C hysteresis; 2 oz copper recommended for both layers; max junction temperature derating limits continuous 2 A output at high ambient | DS41326 Rev 3, Thermal Resistance + Electrical Characteristics, TSD / THYS + PCB Layout section |
| Bootstrap capacitor | 100 nF ceramic capacitor required between BST and SW; boot undervoltage protection refreshes BST cap when voltage falls below 2.3 V by turning Q2 on for 220 ns; BST abs max VSW + 6.0 V | DS41326 Rev 3, Application Information Section 13 Bootstrap Capacitor + Absolute Maximum Ratings, VBST |
| Reference / divider | 0.8 V ±1% internal reference (AP63200/AP63201 adjustable versions); AP63203 is fixed 3.3 V — FB pin connects direct to output, no external divider needed | DS41326 Rev 3, Features + Figure 21 Typical Application Circuit for AP63203/AP63205 |
Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.
Alternatives
- AP63200WU-7: same family, adjustable output from 0.8 V (external divider), 500 kHz switching, PWM/PFM. Choose it when you need a voltage other than 3.3 V or 5 V.
- AP63201WU-7: same family, adjustable output, 500 kHz, forced PWM only — no PFM. Use when the application cannot tolerate variable-frequency light-load ripple (sensitive analog, audio).
- AP63205WU-7: same family, fixed 5.0 V output, 1.1 MHz, PWM/PFM. The 5 V counterpart to the AP63203.
- MP1584EN: the nonsynchronous wide-input buck on countless marketplace modules. Cheaper and adjustable, but needs an external catch diode, has higher quiescent current, and module quality varies wildly.
- TPS5430: TI's non-synchronous wide-input buck (5.5–36 V, 3 A). Higher input voltage ceiling but lower switching frequency (500 kHz) means bigger magnetics, and the external catch diode adds a BOM line and an efficiency penalty at low output voltages.
Common questions
- Does the AP63203 need an external Schottky diode?
- No. It is a fully synchronous buck with both high-side (125 mΩ) and low-side (68 mΩ) MOSFETs integrated on chip. The low-side MOSFET replaces the catch diode — it conducts during the off-time with lower loss than any Schottky. You still need a 100 nF bootstrap capacitor from BST to SW.
- Can I adjust the AP63203 output voltage away from 3.3 V?
- No. The AP63203 is factory-trimmed to a fixed 3.3 V output. The FB pin is a sense pin, not a divider input — connect it directly to the output rail. For adjustable output, use the AP63200 (500 kHz) or AP63201 (500 kHz forced PWM), which provide a 0.8 V ±1% reference with an external resistive divider.
- Why does the AP63203 ripple get larger at light load?
- The AP63203 operates in PFM below approximately 450 mA peak inductor current. In PFM the converter skips switching cycles and the output ripple amplitude increases. This is normal operation — it trades ripple for efficiency (up to 88% at 5 mA). If your load cannot tolerate the larger ripple, use the AP63201 (forced PWM) variant or add more output capacitance.
- What input capacitor does the AP63203 need?
- Diodes recommends 10 µF ceramic on the input (Table 2). The RMS current rating must exceed half the maximum load current. Place it as close to the VIN and GND pins as possible — the datasheet's PCB layout guide calls this out explicitly. For higher input voltages or hotter ambients, consider a larger case size or parallel capacitors to handle the ripple current.
- How hot will the AP63203 get at 2 A?
- At 12 V in, 3.3 V out, 2 A load, the power loss is roughly 0.5–0.7 W. With θJA of 89 °C/W on single-layer FR-4, expect a 44–62 °C junction rise above ambient. The recommended maximum junction temperature is 125 °C, so at 2 A you have headroom at room temperature but derating kicks in above ~60 °C ambient. Use 2 oz copper on both layers, a solid bottom-layer GND pour, and stitch vias through capacitor GND pads to keep the junction cool — exactly as the datasheet Figure 25 layout shows.