TPS5430 PCB Design Guide: Footprint, Pinout, and Alternatives
Wide-input 5.5–36 V, 3 A nonsynchronous buck converter with on-chip compensation.
The TPS5430 is TI's wide-input step-down converter: 5.5 V to 36 V in, up to 3 A continuous (4 A peak) out, built around a 100 mΩ integrated high-side MOSFET switching at a fixed 500 kHz. The loop compensation is on chip, the output is set by a two-resistor divider against a 1.221 V reference, and efficiency reaches 95% with a well-chosen catch diode. The whole regulator is an 8-pin SO PowerPAD plus a handful of external parts, which is why it has been a default answer for getting a logic rail off a rough industrial supply since the datasheet first appeared in January 2006.
The tradeoffs are all about what is not on the chip. It is nonsynchronous, so the low-side switch is an external Schottky you select: cheap and simple, but the diode's forward drop caps efficiency, and there is no synchronous light-load behavior. Internal compensation is the same bargain; it saves parts, but the loop is designed around a specific output-capacitor ESR window, so capacitor substitutions are stability changes, not BOM swaps. Quiescent current is 2 mA, which rules out battery standby duty (shutdown drops to 15 µA), and the 500 kHz frequency is fixed, with no synchronization or adjustment. Pick it for wide, ugly inputs feeding amps of output; pick a modern synchronous buck for tight point-of-load rails or light-load efficiency.
When a TPS5430 design misbehaves, the silicon is rarely the problem. The recurring failures are board-level: a BOOT capacitor rated against the wrong voltage number, a catch diode treated as an afterthought, ceramic output capacitors that quietly break the internal compensation, a PowerPAD that never got soldered, and input-bypass and switch-node layout that ignores the datasheet's placement rules. Each is covered below.
What breaks boards
Rate the BOOT capacitor for 10 V, not the 6 V absolute maximum
The BOOT-to-PH absolute maximum reads 6 V, but a note added in Rev. L says some devices develop above 6 V (below 10 V) across this pair in normal operation, without damage to the IC. The capacitor is another matter: TI requires any capacitor between BOOT and PH to be rated for at least 10 V operation. Use the specified 0.01 µF low-ESR ceramic in X7R or X5R, and select its voltage rating against 10 V, not against the abs-max table. A part chosen for a 6 V line is a latent field failure.
There is no low-side FET: the catch diode is a design decision
The TPS5430 is nonsynchronous. Only the high-side MOSFET is on chip; an external Schottky from PH to GND carries the inductor current every off-time. Its reverse rating must exceed VIN(MAX) + 0.5 V — TI's example design uses a 40 V B340A (3 A, 0.5 V forward drop) — and its peak-current rating must beat IOUT(MAX) plus half the peak-to-peak inductor ripple. At low duty cycles the diode conducts longer than the FET does, so its forward drop, not the 100 mΩ switch, sets efficiency. The up-to-95% headline assumes a good Schottky.
The output capacitor's ESR is part of the control loop
The type 3 compensation is internal and was designed around capacitors like the 220 µF, 40 mΩ-max-ESR POSCAP in TI's example: the ESR zero must sit above the loop crossover, which TI wants between 3 kHz and 30 kHz, and not far above the internal poles at 24 kHz and 54 kHz. Swap in low-ESR ceramics as an upgrade and the phase margin collapses; the classic symptom is output oscillation under load. All-ceramic outputs are supported, but only with the datasheet's external compensation network and an LC resonant frequency no higher than 7 kHz.
The PowerPAD is both the ground connection and the heatsink
The GND pin must be connected to the exposed pad for proper operation, and the pad must be soldered to a topside ground pour stitched with vias — this is electrical, not just thermal. Junction-to-case (bottom) is 6 °C/W while the EVM's junction-to-ambient is 45 °C/W, so essentially all the heat leaves through that pad. Skip the paste aperture or the vias and a 3 A design cycles through thermal shutdown, which trips at 162 °C typical (135 °C minimum) and restarts after cooling 14 °C. A converter that hiccups under load often has an unsoldered DAP.
Put the VIN bypass within 1 mm and keep the PH copper small
Rev. L quantifies input bypass placement: a low-ESR ceramic within 1 mm of the VIN pin and within 1 mm of the GND pin, minimum 4.7 µF in X5R or X7R (the design examples use 10 µF for decoupling). The input loop of a nonsynchronous buck carries fast discontinuous current, and a long loop shows up as PH-node ringing and EMI. PH itself wants minimum copper area: place the inductor and catch diode tight against the pin, and route the VSENSE divider trace away from PH — under the output capacitor or on another layer.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Input voltage range | 5.5 V min / 36 V max (TPS5430; TPS5431 variant: 5.5 V min / 23 V max) | SLVS632L Rev L, Section 5.3 Recommended Operating Conditions |
| Output current | Up to 3A continuous (4A peak) output current | SLVS632L Rev L, Section 1 Features |
| Switching frequency | 400 kHz min / 500 kHz typ / 600 kHz max (fSW) | SLVS632L Rev L, Section 5.5 Electrical Characteristics, Oscillator |
| Feedback reference | 1.221 V typ; 1.202 V min / 1.239 V max at TJ = 25 degC; 1.196 V min / 1.245 V max at TJ = -40 degC to 125 degC | SLVS632L Rev L, Section 5.5 Electrical Characteristics, Voltage Reference (VFB) |
| High-side RDS(on) | 100 mOhm typ / 230 mOhm max (VIN = 12 V, VBOOT-SW = 4.5 V); 125 mOhm typ (VIN = 5.5 V, VBOOT-SW = 4.0 V) | SLVS632L Rev L, Section 5.5 Electrical Characteristics, Output MOSFET (RDSON(HS)) |
| Quiescent / shutdown current | IQ(VIN) 2 mA typ / 4.4 mA max (non-switching, VSENSE = 2V, PH pin open); ISD(VIN) 15 uA typ / 50 uA max (shutdown, ENA = 0V) | SLVS632L Rev L, Section 5.5 Electrical Characteristics, Supply Voltage (VIN pin) |
| Min ON time / max duty | Minimum ON pulse width 150 ns typ / 200 ns max; maximum duty cycle 87% min / 89% typ (fSW = 500 kHz) - min on-time limits achievable step-down ratio at 500 kHz; min duty limits low-VOUT-from-high-VIN designs | SLVS632L Rev L, Section 5.5 Electrical Characteristics, Oscillator (tON(min), DMAX) |
| Efficiency | High efficiency up to 95% enabled by 100 mOhm integrated MOSFET switch (front-page curve conditions: VI = 12 V, VO = 5 V, fs = 500 kHz, TA = 25 degC) | SLVS632L Rev L, Section 1 Features + Efficiency vs Output Current front-page curve |
| UVLO | VIN UVLO rising threshold 5.3 V typ / 5.5 V max; UVLO hysteresis 0.35 V typ | SLVS632L Rev L, Section 5.5 Electrical Characteristics, UVLO |
| BOOT capacitor | 0.01 uF low-ESR ceramic (X7R or X5R recommended) from BOOT to PH; BOOT to PH absolute maximum is 6 V, but some devices develop voltage above 6 V (below 10 V) during operation without damage, so capacitors placed between BOOT and PH must be rated for at least 10 V operation | SLVS632L Rev L, Section 5.1 Absolute Maximum Ratings note 3 + Section 6.3.5 Boost Capacitor (BOOT) + Table 4-1 Pin Functions |
| Catch diode | Nonsynchronous: external catch diode from PH to GND required; reverse voltage must be higher than VIN(MAX) + 0.5 V, peak current greater than IOUT(MAX) plus one half the peak-to-peak inductor current; design example uses a Diodes Inc. B340A (40 V reverse voltage, 3 A forward current, 0.5 V forward drop) | SLVS632L Rev L, Section 7.2.1.2.7 Catch Diode + Simplified Schematic |
| Loop compensation | Internal voltage-mode type 3 compensation; closed-loop crossover frequency should be kept in the range 3 kHz to 30 kHz; internal compensation poles at 24 kHz and 54 kHz; design example output capacitor 220 uF with 40 mOhm maximum ESR (Sanyo POSCAP 10TPB220M); all-ceramic output filters require the external compensation network and an LC resonant frequency of no more than 7 kHz | SLVS632L Rev L, Section 7.2.1.2.4.2 Capacitor Selection + Section 7.2.1.2.8.2 Internal Compensation Network + Section 7.2.3.2.1 Output Filter Component Selection |
| Thermal | RthetaJA 45 degC/W (TPS5430EVM); RthetaJC(bot) 6 degC/W; thermal shutdown threshold 135 degC min / 162 degC typ (temperature rising) with 14 degC hysteresis; GND pin must be connected to the exposed pad (DAP) for proper operation | SLVS632L Rev L, Section 5.4 Thermal Information (DDA Package) + Section 5.5 Electrical Characteristics, Thermal Shutdown + Table 4-1 Pin Functions (DAP) |
| Input bypass | Bypass VIN to GND close to the device package with a high quality, low ESR ceramic capacitor placed within 1 mm of the VIN pin and within 1 mm of the GND pin; minimum recommended bypass capacitance 4.7 uF ceramic with X5R or X7R dielectric; design example decoupling capacitor 10 uF | SLVS632L Rev L, Table 4-1 Pin Functions (VIN) + Section 7.4.1 Layout Guidelines + Section 7.2.1.2.3 Input Capacitors |
| Output voltage setting | Resistor divider from VOUT to VSENSE against the 1.221 V reference; R2 = R1 x 1.221 / (VOUT - 1.221), start with R1 = 10 kOhm; minimum output voltage is the internal 1.221 V feedback reference | SLVS632L Rev L, Section 7.2.1.2.5 Output Voltage Set-Point (Equation 12) + Section 6.1 Overview |
Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.
Alternatives
- TPS5431: same datasheet and package, with the input range limited to 5.5–23 V instead of 5.5–36 V. Only worth speccing when the supply genuinely cannot exceed its rating; the 36 V part is the safer default.
- MP1584EN: the low-cost wide-input buck on countless marketplace modules. Fine for bench rails, but module layout and capacitor quality vary wildly, and thermals under sustained load depend entirely on the module.
- LM2596S-ADJ: an older adjustable wide-input buck, everywhere on cheap modules. Its much lower switching frequency means bulkier magnetics and slower transient response than the TPS5430.
- TPS5430-Q1: the AEC-Q100 automotive-qualified version, listed as a qualified version in TI's Package Option Addendum. The part to spec when the design needs automotive qualification paperwork.
Common questions
- Does the TPS5430 need an external diode?
- Yes. It is a nonsynchronous buck with only the high-side MOSFET integrated, so a catch diode from PH to GND is mandatory. Rate its reverse voltage above VIN(MAX) + 0.5 V and its peak current above the maximum load current plus half the inductor ripple; TI's example design uses a 40 V, 3 A B340A Schottky. The diode's forward drop directly sets efficiency.
- Can the TPS5430 run from a 5 V rail?
- No. The recommended minimum input is 5.5 V, and the UVLO rising threshold is 5.3 V typical (5.5 V max) with 0.35 V of hysteresis, so a nominal 5 V rail sits below the guaranteed start voltage. The TPS5431 variant lowers the maximum input to 23 V but keeps the same 5.5 V minimum. For 5 V inputs, pick a buck specified to start below that rail.
- Can I use ceramic output capacitors with the TPS5430?
- Yes, but not as a drop-in. The internal compensation expects the ESR zero of tantalum/polymer-class output capacitors. With an all-ceramic output you must add the external compensation network from the datasheet's ceramic-output design example and keep the output LC resonant frequency at or below 7 kHz. Without it, expect oscillation.
- How do I set the TPS5430 output voltage, and what is the minimum?
- With a resistor divider from VOUT to VSENSE against the 1.221 V internal reference: start with R1 = 10 kΩ on top and compute R2 = R1 × 1.221 / (VOUT − 1.221). The minimum output voltage is the reference itself, 1.221 V; the top end is constrained by the 87% minimum-guaranteed duty cycle.