DRV8825 PCB Design Guide: Footprint, Pinout, and Alternatives
8.2–45 V bipolar stepper driver with a built-in 1/32 microstepping indexer and STEP/DIR control.
The DRV8825 is TI's workhorse bipolar stepper driver: two N-channel H-bridges, PWM current chopping, and an on-chip microstepping indexer that runs from full step down to 1/32 microstep, all controlled through a two-pin STEP/DIR interface. It takes a single 8.2 to 45 V motor supply and delivers up to 2.5 A per winding, a figure TI conditions on proper heat sinking at 24 V and 25 °C. A dedicated nSLEEP pin drops supply current to 10 µA typical, and overcurrent, overtemperature, and undervoltage protection report on an open-drain nFAULT pin. This is the chip on the ubiquitous purple stepper breakouts in 3D printers and hobby CNC machines.
Pick the DRV8825 over the older A4988 when you want the higher 45 V supply ceiling or 1/32 microstepping instead of 1/16; the STEP/DIR interface and the common breakout footprint are interchangeable. Pick something else when acoustics matter: this is a plain fixed-frequency chopper with three decay modes selected by a pin, so it will never match a Trinamic StealthChop part for quiet, and it has no UART or SPI, no stall detection, and no way to reconfigure anything without touching hardware. Be honest about current, too: 2.5 A is a thermally conditioned maximum, not what a bare breakout with a stick-on heatsink will sustain.
The failure modes below are the ones that fill forum threads: supplies under the 8.2 V UVLO floor that make the chip play dead, PowerPAD layouts that hit thermal shutdown long before the rated current, motor hot-plugging that kills the bridge FETs against a 47 V absolute maximum, current settings that wreck microstep accuracy near the zero crossings, and bring-up mistakes with nSLEEP timing and minimum STEP pulse widths.
What breaks boards
It does not run below 8.2 V, and UVLO sits exactly at the minimum supply
The recommended motor supply starts at 8.2 V, and the undervoltage lockout threshold is 7.8 V typical but 8.2 V maximum on rising VM — worst case, UVLO releases right at the minimum operating voltage. A 5 V rail is hopeless, and a nominal supply barely above the floor that sags under motor load will trip UVLO, which disables everything and resets the internal logic, losing indexer position. Give the supply real margin above 8.2 V, and remember all VM pins must be connected to the same supply.
2.5 A is a heat-sinking promise: solder the PowerPAD or derate hard
TI's 2.5 A rating is conditioned on proper heat sinking at 24 V and 25 °C. Dissipation lives in the bridge FETs — 0.2 Ω typical per FET at 25 °C, rising to 0.25 Ω typical and 0.32 Ω maximum at a junction temperature of 85 °C, so losses climb as the die heats. The 31.6 °C/W junction-to-ambient figure assumes a JEDEC high-K board with the PowerPAD soldered down; skip the pad or the via stitching to a ground plane and you hit the 160 °C typical thermal shutdown far below rated current. Shutdown auto-resumes as the die cools, so the symptom is a motor that stutters rhythmically under load.
45 V operating max, 47 V absolute max: almost no headroom for transients
The absolute maximum on VM is 47 V against a 45 V operating maximum, and Rev. F added a 1 V/µs limit on supply ramp rate. Stepper windings are inductive: hot-plugging the motor supply through long leads, or unplugging a winding while energized, produces flyback transients that erase that margin and kill the output FETs. Never connect or disconnect the motor with VM applied. Bypass VMA and VMB locally with ceramics and size the bulk capacitance for the motor's current dumps — an undersized bulk cap lets deceleration pump the rail up toward the absolute maximum.
Current-trip accuracy collapses at low settings: ±5% at full scale, ±25% at 5%
Full-scale winding current is set by the xVREF pins and the sense resistors: the chopper trips when the sense voltage, amplified by the 5 V/V gain, reaches the DAC output — 660 mV typical at the sense pin with VREF at 3.3 V and the 100% setting. Keep VREF inside the recommended 1 to 3.5 V range; it operates between 0 and 1 V but accuracy is degraded, so reach low motor currents with larger sense resistors, not a tiny VREF. Even then, trip accuracy is ±5% at the 71 to 100% settings but ±25% at the 5% setting, which is why the finest microsteps near zero crossings look ragged.
Dead outputs at bring-up: nSLEEP and nRESET idle low, and STEP has timing floors
The logic inputs are held low by internal pulldowns — 100 kΩ on DIR, STEP, nRESET, and MODEx, roughly 1 MΩ on nSLEEP — so floating nSLEEP or nRESET leaves the part asleep or in reset with the outputs high-impedance. Both must be driven high for operation. In firmware, respect the timing table: STEP pulses need 1.9 µs minimum high and low time (a fast MCU toggling a GPIO in a tight loop can violate this), step frequency tops out at 250 kHz, and after releasing nSLEEP the driver needs up to 1.7 ms before it accepts a STEP — pulses sent earlier are silently ignored, which means lost position.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Operating supply voltage | V(VMx) motor power supply voltage range 8.2 V min to 45 V max (all VM pins must be connected to the same supply voltage); absolute maximum -0.3 to 47 V, power supply ramp rate 1 V/us max | SLVSA73F Rev F, Section 7.3 Recommended Operating Conditions + Section 7.1 Absolute Maximum Ratings |
| Output drive current | 2.5-A maximum drive current at 24 V and TA = 25 degC (with proper heat sinking); continuous motor drive output current 0 to 2.5 A absolute maximum (power dissipation and thermal limits must be observed); peak motor drive output current, t < 1 us, internally limited | SLVSA73F Rev F, Section 1 Features + Section 3 Description + Section 7.1 Absolute Maximum Ratings |
| RDS(on) | HS FET on resistance 0.2 ohm typ (V(VMx) = 24 V, IO = 1 A, TJ = 25 degC), 0.25 typ / 0.32 ohm max at TJ = 85 degC; LS FET on resistance identical (0.2 typ at 25 degC; 0.25 typ / 0.32 max at 85 degC) | SLVSA73F Rev F, Section 7.5 Electrical Characteristics, H-BRIDGE FETS |
| Supply current | IVM VM operating supply current 5 mA typ / 8 mA max (V(VMx) = 24 V); IVMQ VM sleep mode supply current 10 uA typ / 20 uA max (V(VMx) = 24 V) | SLVSA73F Rev F, Section 7.5 Electrical Characteristics, POWER SUPPLIES |
| UVLO threshold | VUVLO VM undervoltage lockout voltage 7.8 V typ / 8.2 V max, V(VMx) rising - UVLO max equals the 8.2 V minimum operating supply, so the part is not usable below 8.2 V | SLVSA73F Rev F, Section 7.5 Electrical Characteristics, PROTECTION CIRCUITS + Section 7.3 Recommended Operating Conditions |
| STEP timing | fSTEP step frequency 250 kHz max; tWH(STEP)/tWL(STEP) pulse duration STEP high/low 1.9 us min; tWAKE wakeup time, nSLEEP inactive high to STEP input accepted, 1.7 ms max | SLVSA73F Rev F, Section 7.6 Timing Requirements |
| Current regulation accuracy | VTRIP xISENSE trip voltage 635/660/685 mV min/typ/max (V(xVREF) = 3.3 V, 100% current setting); current trip accuracy Delta-ITRIP +/-5% (71% to 100% setting) degrading to +/-25% (5% setting); current sense amplifier gain 5 V/V (reference only) | SLVSA73F Rev F, Section 7.5 Electrical Characteristics, CURRENT CONTROL |
| Microstepping | Built-in microstepping indexer, up to 1/32 microstepping; MODE0 through MODE2 pins set the step mode - full step (2-phase excitation) with 71% current, 1/2 step, 1/4 step, 8 microsteps/step, 16 microsteps/step, 32 microsteps/step | SLVSA73F Rev F, Section 1 Features + Section 8.3.5 Microstepping Indexer, Table 1 Stepping Format |
| VREF input voltage | V(VREF) VREF input voltage 1 V min to 3.5 V max; operational at VREF between 0 and 1 V, but accuracy is degraded | SLVSA73F Rev F, Section 7.3 Recommended Operating Conditions |
| Thermal | RthetaJA junction-to-ambient thermal resistance 31.6 degC/W (HTSSOP PWP package, JEDEC high-K board per JESD51-7); RthetaJC(bot) junction-to-case (bottom) thermal resistance 1.4 degC/W through the exposed PowerPAD; thermal shutdown temperature 150 min / 160 typ / 180 max degC, die temperature | SLVSA73F Rev F, Section 7.4 Thermal Information + Section 7.5 Electrical Characteristics, PROTECTION CIRCUITS |
| Logic inputs | VIL input low voltage 0 to 0.7 V; VIH input high voltage 2.2 to 5.25 V; DIR, STEP, nRESET and MODEx have internal 100-kOhm pulldown resistors, nSLEEP approximately 1 MOhm - nSLEEP and nRESET must be driven logic high for device operation | SLVSA73F Rev F, Section 7.5 Electrical Characteristics, LOGIC-LEVEL INPUTS + Section 8.3.5 (Table 2 note) + Section 8.3.6 nRESET, nENBL, and nSLEEP Operation |
Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.
Alternatives
- A4988: the incumbent on Pololu-style breakouts: 8-35 V and 2 A max with up to 1/16 microstepping. Lower voltage ceiling and half the microstep resolution of the DRV8825, but the breakout footprints are interchangeable, so boards often accept either.
- TMC2208/TMC2209: Trinamic (Analog Devices) drivers with StealthChop quiet stepping and UART configuration; pin-compatible breakouts are the standard quiet drop-in upgrade in 3D printers. More capable and more expensive; pick the DRV8825 when noise doesn't matter and simplicity does.
- DRV8824: TI same-family part with the same HTSSOP-28 pinout and STEP/DIR interface at a lower 1.6 A drive current. One layout can serve both when smaller motors don't need the full current.
- DRV8833: TI's low-voltage dual H-bridge. No microstepping indexer — you drive the bridges yourself — but it works from supplies far below the DRV8825's 8.2 V floor, which the DRV8825 cannot do at all.
Common questions
- How do I set the winding current on a DRV8825?
- With the xVREF voltage and the sense resistors. The chopper trips when the sense-resistor voltage, amplified by the internal 5 V/V gain, reaches the current DAC's output; at the 100% setting with VREF at 3.3 V the trip voltage is 660 mV typical. Keep VREF in the recommended 1 to 3.5 V range — below 1 V the part still runs but accuracy is degraded — and use larger sense resistors, not a tiny VREF, to reach low currents.
- Can a 3.3 V microcontroller drive the DRV8825 directly?
- Yes. The logic inputs specify VIH at 2.2 V minimum (tolerating up to 5.25 V) and VIL at 0.7 V maximum, so both 3.3 V and 5 V logic work without level shifting. Keep STEP pulses at least 1.9 µs high and low, and drive nSLEEP and nRESET high or the internal pulldowns will hold the part disabled.
- Why won't my DRV8825 run from 5 V?
- Undervoltage lockout. The UVLO threshold is 7.8 V typical and up to 8.2 V maximum, matching the 8.2 V minimum operating supply, so below that everything is disabled and the logic held in reset. There is no low-voltage mode; for sub-8.2 V supplies use a low-voltage driver like the DRV8833 instead.
- What is the maximum step rate of the DRV8825?
- 250 kHz on the STEP pin, with a minimum pulse width of 1.9 µs high and low. Remember that finer microstep modes need proportionally more pulses per revolution, so 1/32 stepping eats into that budget fastest, and that after waking from sleep the driver ignores STEP edges for up to 1.7 ms.