ADS1115 PCB Design Guide: Footprint, Pinout, and Alternatives
16-bit I2C delta-sigma ADC with PGA, comparator, and a four-input mux.
The ADS1115 is TI's 16-bit delta-sigma ADC with an I2C interface, internal reference and oscillator, a PGA spanning full-scale ranges from ±0.256 V to ±6.144 V, and an input mux that provides four single-ended or two differential channels into one converter. It runs from 2 to 5.5 V, converts at 8 to 860 SPS, and draws 150 µA typical while converting, dropping to 0.5 µA typical in power-down. That combination is why it is the standard answer for adding real analog measurement to a microcontroller with weak or absent ADC pins. The current datasheet is SBAS444E (Rev. E, December 2024), shared across the ADS1113/ADS1114/ADS1115 family.
Pick the ADS1115 for slow, precise measurements: load cells through an amplifier, thermistors, current shunts, battery voltages. It is a precision converter, not a fast one; 860 SPS is the ceiling, and every channel shares the single ADC core, so scanning divides that rate further. There is no external-reference option, so gain accuracy is whatever the internal reference delivers: 0.01 % typ / 0.15 % max gain error with 5 ppm/°C typical drift at FSR = ±2.048 V, which is genuinely good but not adjustable. If you need speed, the 12-bit ADS1015 runs 3300 SPS with the same register map; if you need SPI, the ADS1118 is the counterpart.
Board-level failures with this part are remarkably consistent: someone applies a voltage beyond the supply because the ±6.144 V range setting implies it is allowed, wonders why single-ended readings never use half the code range, reads a stale value right after switching the mux, hangs a high-impedance divider straight on the inputs, or wires ALERT/RDY without the pullup and configuration it needs. Each of these is covered below.
What breaks boards
FSR = ±6.144 V is a scaling setting, not an input rating
The PGA setting only rescales the codes; the pins are still clamped by ESD diodes to the rails. Absolute maximum input is GND − 0.3 V to VDD + 0.3 V, with continuous input current held under ±10 mA, and recommended operation keeps inputs between GND and VDD. On a 3.3 V supply with FSR = ±4.096 V, only signals up to ±3.3 V are measurable; the upper codes are simply unreachable. Sensors that swing above VDD need a divider, and possibly series resistance with Schottky clamps, before they touch these inputs.
Single-ended mode uses half the codes, and can still read negative
For single-ended measurements the mux ties the ADC's negative input to GND internally, so only the positive half of the two's-complement range is used and negative input voltages are off-limits entirely. Differential connections use the full range and add common-mode rejection, which is why they are worth the extra pin. Near 0 V, offset error (±3 LSB typ single-ended at FSR = ±2.048 V) can still produce small negative codes; treat the result as a signed 16-bit value or readings near ground will wrap to huge positive numbers.
After a mux or config change, the first continuous-mode reading is stale
There is one ADC behind the four-input mux. In continuous mode, a config write lets the in-flight conversion finish under the old settings, so the next value you read can belong to the previous channel or PGA range. When scanning, use single-shot conversions or discard one conversion period after each reconfiguration. Do not time that period with a bare delay either: the internal oscillator gives −10 %/+10 % data rate variation at all data rates. Poll the OS bit or use ALERT/RDY as a conversion-ready signal instead.
The inputs are not high-impedance, and there is no anti-alias filter
The switched-capacitor front end presents a finite, PGA-dependent load: differential input impedance falls to 710 kΩ typical on the ±0.512 V and ±0.256 V ranges, and common-mode impedance is about 6 MΩ at ±2.048 V. Hang a high-impedance divider or electrode directly on a pin and you buy a gain error. Buffer high-Z sources with an op amp, and add a first-order RC at the inputs: the internal digital filter's response repeats at multiples of the modulator frequency, so unfiltered out-of-band noise aliases straight into the passband.
ALERT/RDY does nothing out of the box
The pin is open-drain, so without a pullup to VDD you will never see an edge. Even with one, the comparator is disabled by default and the pin idles high until you program thresholds and enable the comparator queue. To use it as a conversion-ready output instead, set the most significant bit of Hi_thresh high and the most significant bit of Lo_thresh low; the part then pulses ALERT/RDY at the end of each conversion in continuous mode. In latching mode, the assertion clears only via a conversion-register read or an SMBus alert response.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Supply range | 2 V min to 5.5 V max (power supply, VDD to GND) | SBAS444E Rev E, Section 5.3 Recommended Operating Conditions |
| Resolution / data rate | 16 bits (no missing codes); data rate 8, 16, 32, 64, 128, 250, 475, 860 SPS (data rate variation -10%/+10%, all data rates) | SBAS444E Rev E, Section 5.5 Electrical Characteristics, System Performance |
| PGA full-scale range | FSR = +/-0.256 V min to +/-6.144 V max (VIN = V(AINP) - V(AINN)); absolute input voltage limited to GND to VDD, and no more than VDD + 0.3V may be applied to the analog inputs | SBAS444E Rev E, Section 5.3 Recommended Operating Conditions, Analog Inputs (incl. note 2) |
| Supply current (operating) | 150 uA typ / 200 uA max at TA = 25C, 300 uA max over temperature (VDD = 3.3V, DR = 8SPS, FSR = +/-2.048V unless otherwise noted) | SBAS444E Rev E, Section 5.5 Electrical Characteristics, Power-Supply, IVDD |
| Supply current (power-down) | 0.5 uA typ / 2 uA max at TA = 25C, 5 uA max over temperature | SBAS444E Rev E, Section 5.5 Electrical Characteristics, Power-Supply, IVDD |
| Offset error | -3 LSB min / +/-1 LSB typ / 3 LSB max (FSR = +/-2.048V, differential inputs); +/-3 LSB typ (FSR = +/-2.048V, single-ended inputs); offset drift over temperature 0.005 LSB/C typ (FSR = +/-2.048V) | SBAS444E Rev E, Section 5.5 Electrical Characteristics, System Performance, offset error rows |
| Gain error and drift | 0.01% typ / 0.15% max (FSR = +/-2.048V, TA = 25C); gain drift over temperature 5 ppm/C typ / 40 ppm/C max (FSR = +/-2.048V) | SBAS444E Rev E, Section 5.5 Electrical Characteristics, System Performance, gain error rows |
| Analog input abs max | GND - 0.3 V min to VDD + 0.3 V max (analog input voltage, AIN0 to AIN3); input current, continuous: -10 mA min to 10 mA max (any pin except power supply pins) | SBAS444E Rev E, Section 5.1 Absolute Maximum Ratings |
| LSB size by FSR | 187.5 uV (FSR = +/-6.144V), 125 uV (+/-4.096V), 62.5 uV (+/-2.048V), 31.25 uV (+/-1.024V), 15.625 uV (+/-0.512V), 7.8125 uV (+/-0.256V) | SBAS444E Rev E, Section 7.3.3, Table 7-1 Full-Scale Range and Corresponding LSB Size |
| Input impedance (typ) | Common-mode: 10 Mohm (FSR = +/-6.144V), 6 Mohm (+/-4.096V, +/-2.048V), 3 Mohm (+/-1.024V), 100 Mohm (+/-0.512V, +/-0.256V); differential: 22 Mohm (+/-6.144V), 15 Mohm (+/-4.096V), 4.9 Mohm (+/-2.048V), 2.4 Mohm (+/-1.024V), 710 kohm (+/-0.512V, +/-0.256V) | SBAS444E Rev E, Section 5.5 Electrical Characteristics, Analog Input |
| I2C addresses | ADDR pin to GND = 1001000b (0x48), VDD = 1001001b (0x49), SDA = 1001010b (0x4A), SCL = 1001011b (0x4B); if SDA is used as the device address, hold SDA low for at least 100 ns after SCL goes low | SBAS444E Rev E, Section 7.5.1.1 I2C Address Selection, Table 7-2 |
| Data format | 16 bits of data in binary 2's-complement format; a positive full-scale (+FS) input produces an output code of 7FFFh and a negative full-scale (-FS) input produces an output code of 8000h; the output clips at these codes for signals that exceed full-scale; single-ended signal measurements only use the positive code range from 0000h to 7FFFh (one-half of the full-scale input voltage range), and because of device offset the ADS111x can still output negative codes when V(AINP) is close to 0V | SBAS444E Rev E, Section 7.5.4 Data Format (incl. note); Section 9.1.2 Single-Ended Inputs |
| Power-on defaults | Config register reset = 8583h: MODE = 1b single-shot mode or power-down state (default), PGA = 010b FSR = +/-2.048V (default), DR = 100b 128SPS (default), COMP_QUE = 11b disable comparator and set ALERT/RDY pin to high-impedance (default) | SBAS444E Rev E, Section 8.1.3 Config Register, Figure 8-5 and Table 8-3 |
Verified against the manufacturer datasheet on 2026-07-10. Confirm the current revision before production use.
Alternatives
- ADS1015: the 12-bit, 3300 SPS sibling: same I2C interface, PGA, comparator, and 2-differential/4-single-ended mux. Choose it when 12 bits suffice and higher data rate matters.
- ADS1114: the same 16-bit, 860 SPS core with PGA and comparator but a single differential (or single-ended) input, in the same packages. Cheaper when one channel is all you need.
- ADS1118: the SPI counterpart: 16-bit, 860 SPS, same 2-differential/4-single-ended mux and PGA, plus an integrated temperature sensor. Choose it when SPI is preferred over I2C.
- ADS1115-Q1: the AEC-Q100 automotive-qualified version, for designs that require qualified parts.
Common questions
- What is the ADS1115's I2C address?
- Set by the ADDR pin: GND gives 0x48, VDD gives 0x49, SDA gives 0x4A, and SCL gives 0x4B, so up to four devices can share one bus with no other hardware. Prefer the GND, VDD, and SCL options; if you tie ADDR to SDA, the datasheet requires SDA to be held low for at least 100 ns after SCL goes low for the address to decode correctly.
- How many channels does the ADS1115 really have?
- One 16-bit converter behind a mux offering four single-ended or two differential inputs. Only one conversion runs at a time, so scanning splits the 860 SPS maximum across the inputs, and in continuous mode the first reading after a mux change still belongs to the old configuration and should be discarded.
- Can the ADS1115 measure negative voltages?
- Only differentially. No pin may go below GND − 0.3 V absolute maximum (recommended operation is GND to VDD), but VIN = AINP − AINN reads negative whenever AINN sits above AINP within the supply range. Single-ended inputs measure from 0 V up only. True bipolar signals must be level-shifted or biased into the supply range first.
- What resolution does the ADS1115 actually deliver?
- 16 bits with no missing codes at all data rates, with LSB size set by the PGA: 187.5 µV at FSR = ±6.144 V down to 7.8125 µV at ±0.256 V. Single-ended measurements use only the positive half of the code range, and offset (±1 LSB typ differential at FSR = ±2.048 V) plus noise set the floor on what is usable.